1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and particularly relates to a semiconductor memory device provided with a decoder circuit for selectively activating a selection line in response to an address signal.
2. Description of the Related Art
In semiconductor memory devices such as SRAMs (static random access memories) and DRAMs (dynamic random access memories), a plurality of memory cells are arranged in matrix form having rows and columns to form a cell array, with each memory cell storing data therein. At the time of read operation and write operation, access is made to a memory cell positioned at the row address and column address specified by an address signal.
In read operation, the address signal is decoded, followed by selectively activating a word line corresponding to the row address selected by the decoding result. Among the plurality of memory cells of the cell array, memory cells connected to the selectively activated word line provide their data to complementary bit lines. A voltage difference generated between the complementary bit lines responsive to the read data is amplified by sense amplifiers. Among the data amplified by the sense amplifiers, data corresponding to the column address selected by the decoding result of the address signal is output to the exterior of the semiconductor memory device as read data. In write operation, data is written from the exterior to the sense amplifier corresponding to a specified column address. Thereafter, the data stored in the sense amplifier is stored in the memory cell connected to a selectively activated word line.
FIG. 1 is a circuit diagram showing the configuration of the last stage of a related-art decoder circuit. The circuit of FIG. 1 includes a NAND circuit 11, PMOS transistors 12-1 through 12-3, and NMOS transistors 13-1 through 13-3. The NAND circuit 11 is the last stage of the decoder circuit that decodes an address signal, and corresponds to a single address. Namely, the selection of a particular address by an address signal results in the output of the NAND circuit 11 being LOW. The PMOS transistor 12-1 and the NMOS transistor 13-1 constitute a first-stage inverter, the PMOS transistor 12-2 and the NMOS transistor 13-2 constituting a second-stage inverter, and the PMOS transistor 12-3 and the NMOS transistor 13-3 constituting a third-stage inverter. The drive power of the transistors is progressively increased from the first inverter to the third inverter. This makes it possible to drive an output signal serving as a word selection signal or column selection signal with a large drive power at high speed.
Conventionally, the transistors that are selected in the output portion of the decoder circuit are implemented by use of transistors having a small threshold value in order to achieve a faster access time. Here, the selected transistors are the transistors that become conductive at the time of selecting the specified address. In the example shown in FIG. 1, the word selection signal (or column selection signal) is set to HIGH and put in a selected state when the output of the NAND circuit 11 is LOW. It thus follows that the PMOS transistor 12-1, the NMOS transistor 13-2, and the PMOS transistor 12-3 are the selected transistors.
In this manner, the transistors that are selected in the output portion of the decoder circuit are implemented by use of transistors having a small threshold value. This shortens a signal delay from the output of the NAND circuit 11 to the word selection signal (or column selection signal), thereby making it possible to drive the selection signal at high speed.    [Patent Document 1] Japanese Patent Application Publication No. 2001-143477    [Patent Document 2] Japanese Patent Application Publication No. 10-275465
In the configuration as described above, the transistors having a small threshold value are turns off at the time of standby (at the time of an unselected state). Unfortunately, transistors having a small threshold value have a problem in that a leak current is large. Namely, a large leak current flows at the time of standby (at the time of an unselected state), resulting in excessive power consumption.
In order to obviate this problem, a transistor having a large threshold value may be inserted between the power supply potential and the source node of the transistors having a small threshold value, and may be turned off to shut off the leak current at the time of standby (at the time of an unselected state). Such configuration, however, requires that the transistor having a large threshold value be made in a large size for the purpose of achieving high-speed operations. This is not preferable as it results in an increase in chip size.
Accordingly, there is a need for a semiconductor memory device which can reduce a leak current in the decoder circuit at the time of an unselected state.